IBM unveils world-first 0.7 nm chip technology, pushing Moore's Law forward

IBM said it had unveiled the world’s first sub-1 nanometer chip technology on June 25, 2026, describing the new node as 0.7 nm, or 7 angstroms, and built on a 3D transistor architecture called nanostack. The company said the prototype can pack nearly 100 billion transistors onto a fingernail-sized chip, about twice the density of its 2 nm chip from 2021, with as much as 50% higher performance or 70% greater energy efficiency. The announcement landed as chipmakers try to keep pace with AI workloads and preserve Moore’s Law, the long-running industry pattern of squeezing more computing power into the same space.

The reason the field had started to look stuck is simple in plain language: when transistors get too small, there is less room to place them, route power and signals around them, and keep neighboring parts from interfering with one another. IBM’s own explanation of nanostack says the approach “builds up, not out,” unlocking the vertical axis instead of relying only on the flat X and Y plane that has carried chip scaling for more than 60 years. IBM also points to an earlier turning point in 1997, when the industry moved from aluminum to copper interconnects, as one of the breakthroughs that let chips get smaller and faster before the next wall came into view.

IBM’s latest move follows a line of earlier work that made the sub-1 nanometer claim possible. The company unveiled its first 2 nm-class chip in 2021. In June 2024, IBM and Rapidus Corporation announced a chiplet packaging partnership for 2 nm-generation semiconductors, and in December 2024 they said selective layer reductions had helped solve manufacturing problems in 2 nm nanosheet transistors, including multi-Vt integration and narrow N-P boundary issues. IBM Research said that work was aimed at helping produce 2 nm and beyond at scale within the decade.

If IBM can scale nanostack beyond the lab, the payoff would be measured in more than bragging rights. The company’s own projections point to roughly 50% area scaling, 50% better performance at the same power, or about 70% lower power for the same performance compared with 2 nm technology. That matters for AI training and inference, where electricity and heat have become major limits, and for consumer devices that need more speed without draining batteries faster. The bigger question now is whether stacked 3D transistors can move from a prototype to a manufacturing method broad enough to extend the industry’s scaling path into the next decade.